A serial data communication interface comprises a data bus operating in accordance with a data communication protocol to transfer data serially, i.e., one bit at a time, from one device to another. A well known family of serial data communication interfaces, sometimes referred to as Serial Peripheral Interface or SPI, includes at least three signal lines: Data, Clock and Select. Although these signal lines are commonly referred to as Data, Clock and Select, alternative names, such as Enable instead of Select, are also used. Various types of serial data communication interfaces having so-called “4-wire,” “3-wire,” “2-wire” and even “1-wire” data buses are known, where the term “wire” is a colloquial reference to a signal line. In actuality, the signal line may be a wire, a printed circuit board trace, an optical fiber, or other such single-channel signal-carrying medium. The term “Serial Peripheral Interface” or “SPI” is commonly used to refer to a 3-wire interface having a bidirectional Data line along with the Clock and Select lines, although in some instances the term has been used to refer to a 4-wire interface having two unidirectional Data lines along with the Clock and Select lines. Some SPI busses also include a Reset line.
The SPI is commonly used in electronic systems in which a relatively complex digital subsystem, such as one having a microprocessor, controls aspects of the operation of a peripheral device or other subsystem that is more basic or otherwise different from the controlling digital subsystem. For example, some digital subsystems use a SPI to control another subsystem that primarily comprises analog circuitry, such as radio frequency (RF) circuitry. As illustrated in FIG. 1, a mobile telephone handset 10 commonly comprises an RF subsystem 12 that includes radio transceiver circuitry, a baseband subsystem 14 that includes a microprocessor or similar circuitry for controlling the overall functionality of the handset, and a user interface 16 that includes a microphone, speaker, display, keypad, etc. The RF subsystem 12 receives, downconverts, and demodulates RF signals received through an antenna 18 and provides the demodulated signal 20 in digital form to baseband subsystem 14. Conversely, RF subsystem 12 receives digital signals 22 from baseband subsystem 14, modulates and upconverts them to RF for transmission, and provides the RF signals to antenna 18. Baseband subsystem 14 can modify various operating parameters of RF subsystem 12, such as transmission power levels and modulation modes, by sending instructions to RF subsystem 12 via an SPI bus 24. Baseband subsystem 14 can send such instructions to RF subsystem 12 by performing write operations on SPI bus 24 under control of an SPI controller (not shown in FIG. 1) in baseband subsystem 14.
As illustrated in FIG. 2, the above-referenced SPI controller is commonly referred to as an SPI “master” controller 26 because it is common to control two or more devices or two or more blocks of circuitry within a device. For example, RF subsystem 12 can include two or more RF integrated circuit (IC) chips 28, 30, etc., each of which can be individually controlled by SPI master controller 26. Each of RF IC chips 28, 30, etc., includes a corresponding SPI slave controller 32, 34, etc., that responds to the read and write operations initiated by SPI master controller 26. Each of SPI slave controllers 32, 34, etc., has a unique device identifier associated with it that allows SPI master controller 26 to address it on SPI bus 24. Accordingly, SPI master controller 26 controls the state of the Select signal line and Clock signal line on SPI bus 24 and also controls the state of the Data signal line during write operations. During read operations, the one of SPI slave controllers 32, 34, etc., being read from controls the state of the Data signal line. As described in further detail below with regard to timing diagrams illustrating several SPI protocols, in a data write or data read operation successive data bits are sent in serial format on the Data signal line in synchronism with successive cycles of the Clock signal. In accordance with each of the SPI protocols described below, the Clock signal is activated or asserted during the write or read operation and deactivate or de-asserted when no write or read operation is occurring. Although not shown in FIGS. 1-2, each of SPI slave controllers 32, 34, etc., interfaces with other circuitry, such as the aforementioned controllable analog circuitry, in its respective RF IC chip 28, 30, etc.
Several types of well-known SPI protocols are illustrated by means of the timing diagrams of FIGS. 3-8. As illustrated in FIGS. 3-4, in accordance with one such protocol, a SPI master controller (not shown) of the type described above with regard to FIG. 2 can cause Select to transition from a low logic state or logic-“0” to a high logic state or logic-“1” to indicate a data transfer. The SPI master controller also activates the Clock signal. In some instances a SPI master controller may activate the Clock signal before transitioning the Select signal, and in other instances a SPI master controller may activate the Clock signal after transitioning the Select signal, as indicated by the initial Clock cycle shown in broken line. A SPI protocol in which a data transfer operation begins with Select transitioning from low to high can be referred to as an “active-high select” type of SPI protocol. As illustrated in FIG. 3, the SPI master controller causes the first bit on the Data signal line following the transition of Select from low to a high to be a “0” to indicate that the operation is a write operation. (The label “WbR,” which is equivalent to “ Write/Read” or “Write_bar/Read,” is used in FIG. 3 and similar drawing figures herein to indicate this Write/Read bit.) On each of the next “a” clock cycles following that “0” or write-indicating bit, the SPI master controller can send one address bit (“Aa-1” through “A0”). Then, on each of the next “d” clock cycles following the address bits, the SPI master controller can send one data bit (“Dd-1” through “D0”). Following the transfer of the last data bit D0, the SPI master controller 26 causes Select to transition from high back to low. The number “a” of address bits and the number “d” of data bits are typically fixed or predetermined. That is, during every write operation, the SPI master controller sends the same number “a” of address bits and the same number “d” of data bits as it does during every other write operation. In response to the address and data information, and in accordance with the timing of the transitions of Select and Clock, the one SPI slave controller identified by the address bits (or a portion of the address bits) writes the data to a register (not shown).
As illustrated in FIG. 4, the SPI master controller can cause the first bit on the Data signal line following the transition of Select from a low logic state to a high logic state to be a “1” to indicate that the operation is a read operation. On each of the next “a” clock cycles following that “1” or read-indicating bit, the SPI master controller can send one address bit (“Aa-1” through “A0”). Following the transfer of the last address bit A0, the SPI master controller causes Select to transition from high back to low. Then, after a delay of one or more clock cycles that is commonly referred to a “turn-around time” or “turn-around length,” the SPI slave controller identified by those address bits (or a portion thereof) can read data bits from a register or similar source and send one data bit (“Dd-1” through “D0”) to the SPI master controller on each of “d” clock cycles.
As illustrated in FIGS. 5-6, in accordance with another such protocol, another SPI master controller (not shown) that is generally of the type described above with regard to FIG. 2 can cause Select to transition from high to low to indicate a data transfer. A SPI protocol in which a data transfer operation begins with Select transitioning from high to low can be referred to as an “active-low select” type of SPI protocol.
As illustrated in FIG. 5, the SPI master controller causes the first bit on the Data signal line following the transition of Select from high to low to be a “0” to indicate that the operation is a write operation. On each of the next “a” clock cycles following that “0” or write-indicating bit, SPI master controller 26 can send one address bit (“Aa-1” through “A0”). Then, on each of the next “d” clock cycles following the address bits, the SPI master controller can send one data bit (“Dd-1” through “D0”). Following the transfer of the last data bit D0, the SPI master controller causes Select to transition from a low logic state back to a high logic state. As in the above-described active-high select protocol, the number “a” of address bits and number “d” of data bits are typically fixed or predetermined. In response to the address and data information, and in accordance with the timing of the transitions of Select and Clock, the SPI slave controller identified by the address bits (or a portion of the address bits) writes the data to a register.
As illustrated in FIG. 6, SPI master controller 26 can cause the first bit on the Data signal line following the transition of Select from high to low to be a “1” to indicate that the operation is a read operation. On each of the next “a” clock cycles following that “1” or read-indicating bit, the SPI master controller can send one address bit (“Aa-1” through “A0”). Following the transfer of the last address bit A0, the SPI master controller causes Select to transition from a low logic state back to a high logic state. Then, after a delay of one or more clock cycles (i.e., the turn-around time), the SPI slave controller identified by those address bits (or a portion thereof) can read data bits from a register or similar source and send one data bit (“Dd-1” through “D0”) to the SPI master controller on each of “d” clock cycles.
As illustrated in FIGS. 7-8, in accordance with still another such protocol, still another SPI master controller (not shown) that is generally of the type described above with regard to FIG. 2 can initiate a data transfer without using Select. One such protocol is commonly known as “Inter-Integrated Circuit or “I2C.” Because the I2C protocol does not use Select, the I2C protocol is sometimes referred to as a 2-wire protocol rather than a 3-wire protocol. Although I2C is sometimes described as a separate protocol from SPI, I2C is referred to herein along with the above-described active-high select and active-low select protocols as another type of SPI protocol.
As illustrated in FIG. 7, to indicate the beginning of a data transfer under the I2C protocol, the SPI master controller first causes Data to transition from high to low while Clock is high. Then, to indicate that the data transfer operation is a write operation the SPI master controller holds the Data signal line low (logic-“0”) during the next rising edge of Clock. On each of the next “a” clock cycles following that “0” or write-indicating bit, SPI master controller 26 can send one address bit (“Aa-1” through “A0”). Then, on each of the next “d” clock cycles following the address bits, the SPI master controller can send one data bit (“Dd-1” through “D0”). As in the other protocols described above, the number “a” of address bits and number “d” of data bits are typically fixed or predetermined. The SPI master controller can indicate the end of the data transfer by holding Clock high while causing Data to transition from low to high. In response to the address and data information, and in accordance with the timing of the transitions of Data and Clock, the SPI slave controller identified by the address bits (or a portion of the address bits) writes the data to a register.
As illustrated in FIG. 8, to indicate the beginning of a data transfer under the I2C protocol, the SPI master controller first causes Data to transition from high to low while Clock is high. Then, to indicate that the data transfer operation is a read operation the SPI master controller holds the Data signal line high (logic-“1”) during the next rising edge of Clock. On each of the next “a” clock cycles following that “1” or read-indicating bit, SPI master controller 26 can send one address bit (“Aa-1” through “A0”). Then, after a delay of one or more clock cycles (i.e., the turn-around time), the SPI slave controller identified by those address bits (or a portion thereof) can read data bits from a register or similar source and send one data bit (“Dd-1” through “D0”) to the SPI master controller on each of “d” clock cycles. The SPI master controller can indicate the end of the data transfer by holding Clock high while causing Data to transition from low to high.
In a system in which, for example, SPI slave controller 32 operates in accordance with a first one of the above-described SPI protocols but SPI slave controller 34 operates in accordance with a second one of the above-described SPI protocols, SPI master controller 26 must be capable of switching between the two protocols, i.e., using the first protocol to communicate data with SPI slave controller 32 and using the second protocol to communicate data with SPI slave controller 34. Providing a master controller 26 that operates in accordance with several different protocols can introduce a number of inefficiencies for system manufacturers. Also, providing an RF subsystem 12 that integrates multiple slave controllers operating in accordance with different protocols can be similarly inefficient. It is possible to signal a SPI slave controller circuitry to operate in accordance with a selected SPI protocol by supplying a protocol mode control signal to a mode select pin or similar input on an integrated circuit chip having such a protocol mode select feature. However, dedicating a pin to a protocol mode control signal is wasteful of input/output resources.